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FSM 101 in Mealy state

Author : Kishore Papisetty
fsm style : mealy fsm

verilog code for the sequence detector 101 in mealy state

  module fsm_101(clk,rst,x,z);
input clk,rst,x;
output z;
reg [1:0]pstate,nstate;
reg z;
  always@(x,pstate)
case(pstate)
2'd0:
if(x==1'd1)
begin
nstate<=2'd1;
z<=1'd0;
end
else
begin
nstate<=2'd0;
z<=1'd0;
end
2'd1:
if(x==1'd0)
begin
nstate<=2'd2;
z<=1'd0;
end
else
begin
nstate<=2'd1;
z<=1'd0;
end
2'd2:
if(x==1'd1)
begin
nstate<=2'd1;
z<=1'd1;
end
else
begin
nstate<=2'd0;
z<=1'd0;
end
endcase
  always@(posedge clk)
begin
if(rst==1'd0)
pstate<=2'd0;
else
pstate<=nstate;
end
  endmodule



//TEST BENCH//

`timescale 1ns / 1ps

module fsm_tb;

reg clk;
reg rst;
reg x;

wire z;

fsm_101 uut (
.clk(clk),
.rst(rst),
.x(x),
.z(z)
);

initial begin

clk <=1'd0;
rst <=1'd0;
x <=1'd0;
#100;
        rst<=1'd1;
 #100 x<=1'd1;
 #100 x<=1'd0;
 #100 x<=1'd1;
 #100 x<=1'd1;
 #100 x<=1'd0;
 #100 x<=1'd0;
 #100 x<=1'd1;
 #100 x<=1'd1;
 #100 x<=1'd0;
 #100 x<=1'd0;
 #100 x<=1'd1;
 #100 x<=1'd0;
 #100 x<=1'd1;
 #100 x<=1'd1;
 #100 x<=1'd0;
 #100 x<=1'd1;
 #100 x<=1'd1;
 #100 x<=1'd0;
 #100 x<=1'd0;
 #100 x<=1'd0;
 #100 x<=1'd1;
 end
 always #50 clk <= !clk;



   
endmodule



WAVE FORM ;



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