Gray code counter in VHDL

Author : Kishore Papisetty

code : VHDL


Gray code is the code with only bit transition between adjacent words. The direct description of Gray counter is based on the equation extraction from the truth table.
Such solution of n bit counter demands 2^(n-2). product terms. Implementation may be difficult for greater width of counter. The alternative is using of auxiliary bit.

The design was based on the Auxiliary bit generation.

vhdl code for the gray counter

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gray_counter is
    Port ( clk : in  STD_LOGIC;
           rst : in  STD_LOGIC;
           gray_code : out  STD_LOGIC_VECTOR (3 DOWNTO 0));
end gray_counter;

architecture Behavioral of gray_counter is
signal count:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
begin
process(clk)
begin
if(rst='1')
then
count <= "0000";
elsif(rising_edge(clk))
then
count<=count+"0001";
end if;
end process;
gray_code <= count xor('0'&count(3 DOWNTO 1));


end Behavioral;

testbench for the gray counter

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY gray_conter_tb IS

END gray_conter_tb;

ARCHITECTURE behavior OF gray_conter_tb IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT gray_counter

    PORT(

         clk : IN  std_logic;

         rst : IN  std_logic;

         gray_code : OUT  std_logic_vector(3 downto 0)

        );

    END COMPONENT;

    

   --Inputs

   signal clk : std_logic := '0';

   signal rst : std_logic := '1';

  --Outputs

   signal gray_code : std_logic_vector(3 downto 0);

   -- Clock period definitions

   constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

   uut: gray_counter PORT MAP (

          clk => clk,

          rst => rst,

          gray_code => gray_code

        );

   -- Clock process definitions

   clk_process :process

   begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

   end process;

   -- Stimulus process

   stim_proc: process

   begin

      -- hold reset state for 100 ns.

      wait for 100 ns;

rst<='0';

      wait for clk_period*10;

      -- insert stimulus here 

      wait;

   end process;

END;

The code was generated on the xilinx tool and executed successfully.