full substractor verilog code

Author : Kishore Papisetty

module fullsubtractor(
output diff,
output br,
input a,
input b,
input c
);

assign diff = a^b^c;
assign br = (~a&b)|(~a&c)|(b&c);
endmodule

Comments

FSM 101 in Mealy state

Author : Kishore Papisetty fsm style : mealy fsm verilog code for the sequence detector 101 in mealy state module fsm_101(clk,rst,x,z); input clk,rst,x; output z; reg [1:0]pstate,nstate; reg z; always@(x,pstate) case(pstate) 2'd0: if(x==1'd1) begin nstate<=2'd1; z<=1'd0; end else begin nstate<=2'd0; z<=1'd0; end 2'd1: if(x==1'd0) begin nstate<=2'd2; z<=1'd0; end else begin nstate<=2'd1; z<=1'd0; end 2'd2: if(x==1'd1) begin nstate<=2'd1; z<=1'd1; end else begin nstate<=2'd0; z<=1'd0; end endcase always@(posedge clk) begin if(rst==1'd0) pstate<=2'd0; else pstate<=nstate; end endmodule //TEST BENCH// `timescale 1ns / 1ps module fsm_tb; reg clk; reg rst; reg x; wire z; fsm_101 uut ( ...

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VHDL code for a 3-bit binary to thermometer converter

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VHDL/Verilog Coding

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