verilog code for 4 bit multiplier

Author : Kishore Papisetty

//verilog code for 4 bit multiplier//


module binarymul(
    output [7:0] p,

    input [3:0] a,
    input [3:0] b
    );
assign p[0] = a[0]&b[0];
wire [17:1] x;
wire op1,op2,op3,op4,op5,op6,op7,op8,op9,op10,op11,op12,op13,op14,op15;
and A1(op1,a[1],b[0]);
and A2(op2,a[0],b[1]);
halfadder HA1(p[1],x[1],op1,op2);
and A3(op3,a[1],b[1]);
and A4(op4,a[0],b[2]);
fulladder FA1(x[2],x[3],op3,op4,x[1]);
and A5(op5,a[1],b[2]);
and A6(op6,a[0],b[3]);
fulladder FA2(x[4],x[5],op5,op6,x[3]);
and A7(op7,a[1],b[3]);
halfadder HA2(x[6],x[7],op7,x[5]);
and A8(op8,a[2],b[0]);
halfadder HA3(p[2],x[15],x[2],op8);
and A9(op9,a[2],b[1]);
fulladder FA5(x[14],x[16],x[4],op9,x[15]);
and A10(op10,a[2],b[2]);
fulladder FA4(x[13],x[17],x[6],op10,x[16]);
and A11(op11,a[2],b[3]);
fulladder FA3(x[9],x[8],x[7],op11,x[17]);
and A12(op12,a[3],b[0]);
halfadder HA4(p[3],x[12],x[14],op12);
and A13(op13,a[3],b[1]);
fulladder FA8(p[4],x[11],x[13],op13,x[12]);
and A14(op14,a[3],b[2]);
fulladder FA7(p[5],x[10],x[9],op14,x[11]);
and A15(op15,a[3],b[3]);
fulladder FA6(p[6],p[7],x[8],op15,x[10]);
endmodule

//verilog code half adder//

module halfadder(

    output sum,

    output carry,

input a,

    input b

    

    );

assign sum = a^b;

assign carry = a&b;

endmodule

// verilog codefull adder//

module fulladder(

output sum,

    output carry,

    input a,

    input b,

    input c

    

    );

assign sum = a^b^c;

assign carry = (a&b)|(b&c)|(c&a);

endmodule