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Floating point addition 32 bit

// 32 bit  floating point  addition//

Author : Kishore Papisetty
HDl lagugage; verilog hdl

module fp_add_seq(sum,ready,a_original,b_original,start,clk);
   input [31:0] a_original, b_original;
   input        start, clk;
   output [31:0] sum;
   output        ready;

   reg           sumneg;
   reg [7:0]    sumexp;
   reg [22:0]    sumsig;
   assign  sum [31]    = sumneg;
   assign        sum [30:23] = sumexp;
   assign        sum [22:0]  = sumsig;

   reg [32:0]    a, b;
   reg [22:0]    asig, bsig;
   reg [7:0]    aexp, bexp;
   reg           aneg, bneg;
   reg [7:0]    diff;

   parameter     st_idle  = 0;
   parameter     st_cyc_1 = 1;
   parameter     st_cyc_2 = 2;
   parameter     st_cyc_3 = 3;

   reg [1:0]     state;

 

   assign ready = state == st_idle;

   always @( posedge clk )
     case( state )
       st_idle:
         if ( start ) begin
if ( a_original[30:23] < b_original[30:23] ) begin

               a = b_original;  b = a_original;

            end else begin

               a = a_original;  b = b_original;

            end

            state = st_cyc_1;

         end

       st_cyc_1:
         begin
aneg = a[31];     bneg = b[31];
            aexp = a[30:23];  bexp = b[30:23];
         
            asig = { 2'b0, aexp ? 1'b1 : 1'b0, a[22:0] };
            bsig = { 2'b0, bexp ? 1'b1 : 1'b0, b[22:0] };

            diff = aexp - bexp;
            bsig = bsig >> diff;
         
            state = st_cyc_2;

         end

       st_cyc_2:
         begin

            if ( aneg ) asig = -asig;
            if ( bneg ) bsig = -bsig;

            sumsig = asig + bsig;

            state = st_cyc_3;

         end

       st_cyc_3:
         begin
            sumneg = sumsig[22];
            if ( sumneg ) sumsig = -sumsig;

            if ( sumsig[21] )
begin
             

               sumexp = aexp + 1;
               sumsig = sumsig >> 1;

            end else if ( sumsig ) begin:A
             
               integer pos, adj, i;

             
               pos = 0;
               for (i = 22; i >= 0; i = i - 1 )
                 if ( !pos && sumsig[i] ) pos = i;

             
               adj = 23 - pos;
               if ( aexp < adj ) begin
                  sumexp = 0;
                  sumsig = 0;
                  sumneg = 0;

               end else begin
               

                  sumexp = aexp - adj;
                  sumsig = sumsig << adj;

               end

            end else begin
             
               sumexp = 0;
               sumsig = 0;

            end
end


           default: state = st_idle;

              endcase

endmodule

//test bench //


module faddition_tb;

// Inputs
reg [31:0] a_original;
reg [31:0] b_original;
reg start;
reg clk;

// Outputs
wire [31:0] sum;
wire ready;

// Instantiate the Unit Under Test (UUT)
fp_add_seq uut (
.sum(sum),
.ready(ready),
.a_original(a_original),
.b_original(b_original),
.start(start),
.clk(clk)
);

initial begin
// Initialize Inputs
a_original = 0;
b_original = 0;
start = 0;
clk = 0;

// Wait 100 ns for global reset to finish
#100;
        a_original = 32'b10010100101000000010001000100011;
b_original = 32'b00010010100000000001000000000000;
start = 1'b1;
// Add stimulus here

end
always #100 clk = !clk;

     
endmodule

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