full adder verilog code

Author : Kishore Papisetty

verilog code for full adder

module fulladder(
output sum,
output carry,
input a,
input b,
input c

);

assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule

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Gray code counter in VHDL

Author : Kishore Papisetty code : VHDL Gray code is the code with only bit transition between adjacent words. The direct description of Gray counter is based on the equation extraction from the truth table. Such solution of n bit counter demands 2^(n-2). product terms. Implementation may be difficult for greater width of counter. The alternative is using of auxiliary bit. The design was based on the Auxiliary bit generation. vhdl code for the gray counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gray_counter is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; gray_code : out STD_LOGIC_VECTOR (3 DOWNTO 0)); end gray_counter; architecture Behavioral of gray_counter is signal count:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; begin process(clk) begin if(rst='1') then count <= "0000"...

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full substractor verilog code

Author : Kishore Papisetty module fullsubtractor( output diff, output br, input a, input b, input c ); assign diff = a^b^c; assign br = (~a&b)|(~a&c)|(b&c); endmodule

VHDL/Verilog Coding

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