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verilog code for ripple carry adder

Author : Kishore Papisetty

verilog code for the ripple carry adder i structural format

module ripple(
    output [3:0] s,
    output cout,
input [3:0] a,
    input [3:0] b,
    input cin
   
    );
wire c1,c2,c3;
fulladder F1(s[0],c1,a[0],b[0],cin);
fulladder F2(s[1],c2,a[1],b[1],c1);
fulladder F3(s[2],c3,a[2],b[2],c2);
fulladder F4(s[3],cout,a[3],b[3],c3);

endmodule


verilog code for the full adder

module fulladder(
output sum,
    output carry,
    input a,
    input b,
    input c
   
    );

assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule


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