Author : Kishore Papisetty
//verilog code for the arithmatic logocal unit //
module ALU(
output [7:0]f,
input [3:0] a,
input [3:0] b,
input [1:0] s
);
wire [3:0]q,r;
wire [7:0]p,z,l,k;
wire cout,br,cin,c;
assign cin=1'd0;
assign c=1'd0;
assign z=8'd0;
ripple A1(r,cout,a,b,cin);
subtractor A2(q,br,a,b,c);
binarymul A3(p,a,b);
assign k={3'd0,cout,r[3:0]};
assign l={4'd0,q[3:0]};
mux_21 A5(f,s,p,l,k,z);
endmodule
//TEST BENCH//
module ALU_TB;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg [1:0] s;
// Outputs
wire [7:0] f;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.f(f),
.a(a),
.b(b),
.s(s)
);
initial begin
// Initialize Inputs
a <=4'd0;
b <=4'd0;
s <=2'd0;
// Wait 100 ns for global reset to finish
#100;
#100
s<=2'b00;
a<=4'd5;
b<=4'd4;
#100 s<=2'b01;
a<=4'd4;
b<=4'd4;
#100 s<=2'b10;
a<=4'd15;
b<=4'd4;
#100 s<=2'b11;
// Add stimulus here
end
endmodule
ALU RTL VIEW
WAVEFORM:
//verilog for the subtracor//:
module fullsubtractor(
output diff,
output br,
input a,
input b,
input c
);
assign diff = a^b^c;
assign br = (~a&b)|(~a&c)|(b&c);
endmodule
//verilog code for the arithmatic logocal unit //
module ALU(
output [7:0]f,
input [3:0] a,
input [3:0] b,
input [1:0] s
);
wire [3:0]q,r;
wire [7:0]p,z,l,k;
wire cout,br,cin,c;
assign cin=1'd0;
assign c=1'd0;
assign z=8'd0;
ripple A1(r,cout,a,b,cin);
subtractor A2(q,br,a,b,c);
binarymul A3(p,a,b);
assign k={3'd0,cout,r[3:0]};
assign l={4'd0,q[3:0]};
mux_21 A5(f,s,p,l,k,z);
endmodule
//TEST BENCH//
module ALU_TB;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg [1:0] s;
// Outputs
wire [7:0] f;
// Instantiate the Unit Under Test (UUT)
ALU uut (
.f(f),
.a(a),
.b(b),
.s(s)
);
initial begin
// Initialize Inputs
a <=4'd0;
b <=4'd0;
s <=2'd0;
// Wait 100 ns for global reset to finish
#100;
#100
s<=2'b00;
a<=4'd5;
b<=4'd4;
#100 s<=2'b01;
a<=4'd4;
b<=4'd4;
#100 s<=2'b10;
a<=4'd15;
b<=4'd4;
#100 s<=2'b11;
// Add stimulus here
end
endmodule
ALU RTL VIEW
WAVEFORM:
//verilog for the subtracor//:
module fullsubtractor(
output diff,
output br,
input a,
input b,
input c
);
assign diff = a^b^c;
assign br = (~a&b)|(~a&c)|(b&c);
endmodule
//verilog for the mux//:
module mux_21(
output [7:0]op,
input [1:0]s,
input [7:0]p,
input [7:0]q,
input [7:0]r,
input [7:0]z
);
assign op=s[1]?(s[0]?z:r):(s[0]?q:p);
endmodule
for adder and the multiplier you can found the codes in this blogger with the names ripple carry adder and 4 bit multiplier...
Comments
Post a Comment