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JNTUA MTECH VLSI 2nd SEMESTER QUESTION PAPERS











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VHDL code for a 3-bit binary to thermometer converter

Author : Kishore Papisetty Platform : Xilinx code : VHDL //bit binary to thermometer converter// library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity bin2therm2bit is                 port (                                 binary_input : in std_logic_vector (1 downto 0);                                 therm_output : out std_logic_vector (6 downto 0)                 ); end bin2therm6bit; architecture Behavioral of bin2therm6bit is begin                 process (binary_input)                 begin                                 label1 : case binary_inpu...
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FSM 101 in Mealy state

Author : Kishore Papisetty fsm style : mealy fsm verilog code for the sequence detector 101 in mealy state   module fsm_101(clk,rst,x,z); input clk,rst,x; output z; reg [1:0]pstate,nstate; reg z;   always@(x,pstate) case(pstate) 2'd0: if(x==1'd1) begin nstate<=2'd1; z<=1'd0; end else begin nstate<=2'd0; z<=1'd0; end 2'd1: if(x==1'd0) begin nstate<=2'd2; z<=1'd0; end else begin nstate<=2'd1; z<=1'd0; end 2'd2: if(x==1'd1) begin nstate<=2'd1; z<=1'd1; end else begin nstate<=2'd0; z<=1'd0; end endcase   always@(posedge clk) begin if(rst==1'd0) pstate<=2'd0; else pstate<=nstate; end   endmodule //TEST BENCH// `timescale 1ns / 1ps module fsm_tb; reg clk; reg rst; reg x; wire z; fsm_101 uut ( ...
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