VHDL/Verilog Coding

Author : Kishore Papisetty code : VHDL Gray code is the code with only bit transition between adjacent words. The direct description of Gray counter is based on the equation extraction from the truth table. Such solution of n bit counter demands 2^(n-2). product terms. Implementation may be difficult for greater width of counter. The alternative is using of auxiliary bit. The design was based on the Auxiliary bit generation. vhdl code for the gray counter library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gray_counter is     Port ( clk : in  STD_LOGIC;            rst : in  STD_LOGIC;            gray_code : out  STD_LOGIC_VECTOR (3 DOWNTO 0)); end gray_counter; architecture Behavioral of gray_counter is signal count:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; begin process(clk) begin if(rst='1') then count <= "0000"; elsif(rising_edge(clk)) then count<=count+"

Author : Kishore Papisetty //verilog code for the arithmatic logocal unit // module ALU(     output [7:0]f, input [3:0] a,     input [3:0] b,     input [1:0] s       ); wire [3:0]q,r; wire [7:0]p,z,l,k; wire cout,br,cin,c; assign cin=1'd0; assign c=1'd0; assign z=8'd0; ripple A1(r,cout,a,b,cin); subtractor A2(q,br,a,b,c); binarymul A3(p,a,b); assign k={3'd0,cout,r[3:0]}; assign l={4'd0,q[3:0]}; mux_21 A5(f,s,p,l,k,z); endmodule //TEST BENCH// module ALU_TB; // Inputs reg [3:0] a; reg [3:0] b; reg [1:0] s; // Outputs wire [7:0] f; // Instantiate the Unit Under Test (UUT) ALU uut ( .f(f), .a(a), .b(b), .s(s) ); initial begin // Initialize Inputs a <=4'd0; b <=4'd0; s <=2'd0; // Wait 100 ns for global reset to finish #100; #100 s<=2'b00; a<=4'd5; b<=4'd4;   #100 s<=2'b01; a<=4'd4; b<=4'd4

Author : Kishore Papisetty verilog code for the ripple carry adder i structural format module ripple(     output [3:0] s,     output cout, input [3:0] a,     input [3:0] b,     input cin         ); wire c1,c2,c3; fulladder F1(s[0],c1,a[0],b[0],cin); fulladder F2(s[1],c2,a[1],b[1],c1); fulladder F3(s[2],c3,a[2],b[2],c2); fulladder F4(s[3],cout,a[3],b[3],c3); endmodule verilog code for the full adder module fulladder( output sum,     output carry,     input a,     input b,     input c         ); assign sum = a^b^c; assign carry = (a&b)|(b&c)|(c&a); endmodule

Author : Kishore Papisetty //verilog code for 4 bit multiplier// module binarymul(     output [7:0] p,     input [3:0] a,     input [3:0] b     ); assign p[0] = a[0]&b[0]; wire [17:1] x; wire op1,op2,op3,op4,op5,op6,op7,op8,op9,op10,op11,op12,op13,op14,op15; and A1(op1,a[1],b[0]); and A2(op2,a[0],b[1]); halfadder HA1(p[1],x[1],op1,op2); and A3(op3,a[1],b[1]); and A4(op4,a[0],b[2]); fulladder FA1(x[2],x[3],op3,op4,x[1]); and A5(op5,a[1],b[2]); and A6(op6,a[0],b[3]); fulladder FA2(x[4],x[5],op5,op6,x[3]); and A7(op7,a[1],b[3]); halfadder HA2(x[6],x[7],op7,x[5]); and A8(op8,a[2],b[0]); halfadder HA3(p[2],x[15],x[2],op8); and A9(op9,a[2],b[1]); fulladder FA5(x[14],x[16],x[4],op9,x[15]); and A10(op10,a[2],b[2]); fulladder FA4(x[13],x[17],x[6],op10,x[16]); and A11(op11,a[2],b[3]); fulladder FA3(x[9],x[8],x[7],op11,x[17]); and A12(op12,a[3],b[0]); halfadder HA4(p[3],x[12],x[14],op12); and A13(op13,a[3],b[1]); fulladder FA8(p[4],x[11],x[13],op13,x[12])

Author ; Kishore Papisetty module halfadder(     output sum,     output carry, input a,     input b         ); assign sum = a^b; assign carry = a&b; endmodule

Author : Kishore Papisetty module fullsubtractor(     output diff,     output br,     input a,     input b,     input c     ); assign diff = a^b^c; assign br = (~a&b)|(~a&c)|(b&c); endmodule