VHDL/Verilog Coding

Author : Kishore Papisetty //verilog code for the arithmatic logocal unit // module ALU(     output [7:0]f, input [3:0] a,     input [3:0] b,     input [1:0] s       ); wire [3:0]q,r; wire [7:0]p,z,l,k; wire cout,br,cin,c; assign cin=1'd0; assign c=1'd0; assign z=8'd0; ripple A1(r,cout,a,b,cin); subtractor A2(q,br,a,b,c); binarymul A3(p,a,b); assign k={3'd0,cout,r[3:0]}; assign l={4'd0,q[3:0]}; mux_21 A5(f,s,p,l,k,z); endmodule //TEST BENCH// module ALU_TB; // Inputs reg [3:0] a; reg [3:0] b; reg [1:0] s; // Outputs wire [7:0] f; // Instantiate the Unit Under Test (UUT) ALU uut ( .f(f), .a(a), .b(b), .s(s) ); initial begin // Initialize Inputs a <=4'd0; b <=4'd0; s <=2'd0; // Wait 100 ns for global reset to finish #100; #100 s<=2'b00; a<=4'd5; b<=4'd4;   #100 s<=2'b01; a<=4'd4; b<=4'd4...

Author : Kishore Papisetty verilog code for the ripple carry adder i structural format module ripple(     output [3:0] s,     output cout, input [3:0] a,     input [3:0] b,     input cin         ); wire c1,c2,c3; fulladder F1(s[0],c1,a[0],b[0],cin); fulladder F2(s[1],c2,a[1],b[1],c1); fulladder F3(s[2],c3,a[2],b[2],c2); fulladder F4(s[3],cout,a[3],b[3],c3); endmodule verilog code for the full adder module fulladder( output sum,     output carry,     input a,     input b,     input c         ); assign sum = a^b^c; assign carry = (a&b)|(b&c)|(c&a); endmodule

Author : Kishore Papisetty //verilog code for 4 bit multiplier// module binarymul(     output [7:0] p,     input [3:0] a,     input [3:0] b     ); assign p[0] = a[0]&b[0]; wire [17:1] x; wire op1,op2,op3,op4,op5,op6,op7,op8,op9,op10,op11,op12,op13,op14,op15; and A1(op1,a[1],b[0]); and A2(op2,a[0],b[1]); halfadder HA1(p[1],x[1],op1,op2); and A3(op3,a[1],b[1]); and A4(op4,a[0],b[2]); fulladder FA1(x[2],x[3],op3,op4,x[1]); and A5(op5,a[1],b[2]); and A6(op6,a[0],b[3]); fulladder FA2(x[4],x[5],op5,op6,x[3]); and A7(op7,a[1],b[3]); halfadder HA2(x[6],x[7],op7,x[5]); and A8(op8,a[2],b[0]); halfadder HA3(p[2],x[15],x[2],op8); and A9(op9,a[2],b[1]); fulladder FA5(x[14],x[16],x[4],op9,x[15]); and A10(op10,a[2],b[2]); fulladder FA4(x[13],x[17],x[6],op10,x[16]); and A11(op11,a[2],b[3]); fulladder FA3(x[9],x[8],x[7],op11,x[17]); and A12(op12,a[3],b[0]); halfadder HA4(p[3],x[12],x[14],op12); and A13(op13,a[3],b[1]); ful...

Author ; Kishore Papisetty module halfadder(     output sum,     output carry, input a,     input b         ); assign sum = a^b; assign carry = a&b; endmodule

Author : Kishore Papisetty module fullsubtractor(     output diff,     output br,     input a,     input b,     input c     ); assign diff = a^b^c; assign br = (~a&b)|(~a&c)|(b&c); endmodule

Author : Kishore Papisetty verilog code for full adder module fulladder( output sum,     output carry,     input a,     input b,     input c         ); assign sum = a^b^c; assign carry = (a&b)|(b&c)|(c&a); endmodule

Author : Kishore Papisetty fsm style : mealy fsm verilog code for the sequence detector 101 in mealy state   module fsm_101(clk,rst,x,z); input clk,rst,x; output z; reg [1:0]pstate,nstate; reg z;   always@(x,pstate) case(pstate) 2'd0: if(x==1'd1) begin nstate<=2'd1; z<=1'd0; end else begin nstate<=2'd0; z<=1'd0; end 2'd1: if(x==1'd0) begin nstate<=2'd2; z<=1'd0; end else begin nstate<=2'd1; z<=1'd0; end 2'd2: if(x==1'd1) begin nstate<=2'd1; z<=1'd1; end else begin nstate<=2'd0; z<=1'd0; end endcase   always@(posedge clk) begin if(rst==1'd0) pstate<=2'd0; else pstate<=nstate; end   endmodule //TEST BENCH// `timescale 1ns / 1ps module fsm_tb; reg clk; reg rst; reg x; wire z; fsm_101 uut ( ...

Author : Kishore papisetty module traffic_control(n_lights,s_lights,e_lights,w_lights,clk,rst_a);    output reg [2:0] n_lights,s_lights,e_lights,w_lights;    input      clk;    input      rst_a;    reg [2:0] state;    parameter [2:0] north=3'b000;    parameter [2:0] north_y=3'b001;    parameter [2:0] south=3'b010;    parameter [2:0] south_y=3'b011;    parameter [2:0] east=3'b100;    parameter [2:0] east_y=3'b101;    parameter [2:0] west=3'b110;    parameter [2:0] west_y=3'b111;    reg [2:0] count;    always @(posedge clk, posedge rst_a)      begin         if (rst_a)             begin                 state=north;                 count =3'b000; ...

// 32 bit  floating point  addition// Author : Kishore Papisetty HDl lagugage; verilog hdl module fp_add_seq(sum,ready,a_original,b_original,start,clk);    input [31:0] a_original, b_original;    input        start, clk;    output [31:0] sum;    output        ready;    reg           sumneg;    reg [7:0]    sumexp;    reg [22:0]    sumsig;    assign  sum [31]    = sumneg;    assign        sum [30:23] = sumexp;    assign        sum [22:0]  = sumsig;    reg [32:0]    a, b;    reg [22:0]    asig, bsig;    reg [7:0]    aexp, bexp;    reg           aneg, bneg;    reg [7:0]    diff;    param...

Author : Kishore Papisetty Platform : Xilinx code : VHDL //bit binary to thermometer converter// library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity bin2therm2bit is                 port (                                 binary_input : in std_logic_vector (1 downto 0);                                 therm_output : out std_logic_vector (6 downto 0)                 ); end bin2therm6bit; architecture Behavioral of bin2therm6bit is begin                 process (binary_input)                 begin                                 label1 : case binary_inpu...